A Low-Power CAM with Fully Adiabatic Driving for Match-Lines and Search-Lines

This paper presents a content-addressable memory (CAM) based on adiabatic principle. All circuits except for CAM storage cells and driving control circuits for match-lines are realized using CPAL (complementary pass-transistor adiabatic logic) circuits. The CAM storage cell uses the same structure as convention CMOS circuits with four compare transistors. A fully adiabatic scheme for driving match lines is proposed by using transmission-gates. The charge of large node capacitance on match-lines and bit-lines is well recovered in fully adiabatic manner. In order to reduce energy consumption of the adiabatic CAM during idle periods, a power-gating scheme is used to shut down the address pre-decoder and word-line drivers. SPICE simulations show that the energy loss of the proposed CAM is greatly reduced compared to the conventional CMOS implementation.