DocumentCode
2909470
Title
Efficient floating-point texture decompression
Author
Aarnio, Tomi ; Brunelli, Claudio ; Viitanen, Timo
Author_Institution
Nokia Res. Center, Tampere, Finland
fYear
2010
fDate
29-30 Sept. 2010
Firstpage
31
Lastpage
34
Abstract
We propose a novel hardware design for decoding compressed floating-point textures in a graphics processing unit (GPU). Our decoder is based on the NXR texture format, which provides lossy, fixed-rate 6:1 compression for floating-point textures. Our design exploits the constraints of the compressed pixel blocks to produce the correct output using only fixed-point arithmetic. This results in significantly lower silicon area occupation compared to pre-existing floating-point texture decoders.
Keywords
computer graphics; data compression; floating point arithmetic; hardware-software codesign; NXR texture format; compressed pixel blocks; fixed-point arithmetic; fixed-rate 6:1 compression; floating-point texture decompression; graphics processing unit; hardware design; lower silicon area occupation; Decoding; Dynamic range; Graphics; Hardware; Image coding; Image color analysis; Pixel;
fLanguage
English
Publisher
ieee
Conference_Titel
System on Chip (SoC), 2010 International Symposium on
Conference_Location
Tampere
Print_ISBN
978-1-4244-8279-5
Type
conf
DOI
10.1109/ISSOC.2010.5625555
Filename
5625555
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