Three-dimensional impedance engineering for mixed-signal system-on-chip applications

Author

Chong, Kyuchu ; Zhang, Xi ; Tu, King-Ning ; Huang, Daquan ; Chang, Mau-Chung Frank ; Xie, Ya-Hong

Author_Institution

Dept. of Mater. Sci. & Eng., California Univ., Los Angles, CA

fYear

2005

fDate

21-21 Sept. 2005

Firstpage

663

Lastpage

666

Abstract

An innovative and manufacturable technology for three-dimensional substrate impedance engineering based on p^-/p⁺ Si substrates, which meets the stringent substrate requirement for high performance system-on-chip applications, is described. Electroless plating is used to fabricate Faraday cage for crosstalk isolation and true ground contacts. A self-limiting porous Si formation process is employed from the backside of the wafer. On-chip inductors are situated above the PS allowing for greatly increased Q-factor and resonance frequency

Keywords

Q-factor; electroplating; elemental semiconductors; inductors; mixed analogue-digital integrated circuits; porous semiconductors; silicon; system-on-chip; 3D impedance engineering; Faraday cage; Q-factor; Si formation process; crosstalk isolation; electroless plating; ground contacts; mixed-signal system-on-chip; on-chip inductors; resonance frequency; self-limiting porous; substrate impedance engineering; Crosstalk; Impedance; Inductors; Isolation technology; Manufacturing; Q factor; Resonance; Resonant frequency; System-on-a-chip; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Conference_Location

San Jose, CA

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568757

Filename

1568757