Strain for CMOS performance improvement

Device improvement with strain engineering is considered a way to enhance the carrier mobility. Several stress-transfer techniques (such as etch-stop liner, stress transfer technique, e-SiGe) using extra integration process into an existing baseline process is demonstrated. In addition, new preparation techniques of strained-Si surface (e.g. biaxial tensile stress) and different substrate orientation to enhance mobility are introduced. The challenges and vitality of each method are discussed and compared. In addition, we highlight how the stress oriented from the layout geometry affects the device electrical behavior. The issues and improvement in the circuit level device modeling are discussed.