Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system

High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval (UI). This presents a big problem for the link modeling and verification, especially when link is a part of a larger digital system. We describe here the modeling and simulation method that overcomes this problem. The method is based on a standard hardware description language (HDL) and is applied to a fully adaptive, multi-mode, high-speed serial link system in a 36-channel switch fabric ASIC, designed in 0.13μm CMOS process.