Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers

The systolic array implementation of a block-oriented algorithm known as staged decoding is considered. The staged decoding algorithm is a suboptimal general procedure for decoding a class of signal space codes and lattices obtained through generalized concatenation. By exploiting the trellis representation of block codes and the algebraic formulation of the Viterbi algorithm of G. Fettweis and H. Meyr (1990), the authors derive a very efficient symbol-level pipelined architecture of the staged processor. In order to show the strength of this architecture, they consider the implementation of a staged decoder for an 8-PSK (phase shift keying) BCM (block-coded modulation) scheme with block-length 8 and rate 1 b/dimension. A decoding rate of more than 700 Mb/s with an associated hardware complexity of less than 30 kgates (CMOS, 0.8 μm) has been obtained