Title :
A superconducting ternary systolic array processor
Author :
Morisue, Mititada ; Li, Fu-Qiang
Author_Institution :
Dept. of Electron. Eng., Saitama Univ., Urawa, Japan
Abstract :
A novel Josephson ternary systolic array processor for multiplication is proposed. The processor consists of two kinds of cells, one of which performs a partial multiplication and the other two functions of multiplication and addition simultaneously. The advantages of the processor are its very simple construction with a small number of SQUID gates and its very-high-speed operation and ultralow power dissipation. Information flows between cells in a pipeline fashion so that high performance can be achieved. The principle of the processor is described in detail, and simulation results for the multiplication of 2 trit×2 trit are presented. The results show that the pipeline operation can be executed in a cycle time of 450 ps
Keywords :
digital arithmetic; superconducting processor circuits; systolic arrays; ternary logic; SQUID gates; multiplication; simulation results; superconducting ternary systolic array processor; ultralow power dissipation; very-high-speed operation; Circuit simulation; Computational modeling; Current-voltage characteristics; Equivalent circuits; Josephson junctions; Multivalued logic; Pipelines; SQUIDs; Systolic arrays; Voltage;
Conference_Titel :
Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on
Conference_Location :
Sendai
Print_ISBN :
0-8186-2680-1
DOI :
10.1109/ISMVL.1992.186772
