DocumentCode :
2909946
Title :
A precision CMOS amplifier using floating-gates for offset cancellation
Author :
Srinivasan, Venkatesh ; Serrano, Guillermo J. ; Gray, Jordan ; Hasler, Paul
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA
fYear :
2005
fDate :
21-21 Sept. 2005
Firstpage :
739
Lastpage :
742
Abstract :
A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifier´s architecture. The offset voltage of a single-stage folded cascode amplifier is reduced to plusmn25 muW in a 0.5mum digital CMOS process. The offset voltage drift is 0.5 muV over a period of 10 years at 25degC and varies by a maximum of 130muV over a temperature range of 170degC
Keywords :
CMOS digital integrated circuits; amplifiers; 0.5 micron; 0.5 muV; 10 years; 130 muV; 170 C; 25 C; CMOS amplifier; continuous-time amplifier; digital CMOS; floating-gate transistor; offset cancellation; CMOS process; Capacitors; Circuits; MOSFETs; Operational amplifiers; Prototypes; Sampling methods; Secondary generated hot electron injection; Tunneling; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
Type :
conf
DOI :
10.1109/CICC.2005.1568774
Filename :
1568774
Link To Document :
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