Scan Architecture Modification with Test Vector Reordering for Test Power Reduction

Due to higher switching activity within scan chain for scanning in/out of the vector/response pair, during testing average and peak power dissipation is much higher than the normal mode operation of a circuit. In our paper we propose a method of reducing dynamic power consumption in scan chain by introducing XOR gate at selected places (using genetic algorithm) in the traditional scan chain there by converting D flip-flops into T flip-flops temporarily during scan. This approach involves reordering of test vectors but not reordering of the scan cells. Our proposed method is verified with ISCAS89 benchmark circuits, which shows that upto 24% reduction in switching activity within modified scan architecture is possible.