Title :
Aliasing in multiple-valued test data compaction
Author :
Edirisooriya, Geetani ; Robinson, John P.
Author_Institution :
Iowa Univ., Iowa City, IA, USA
Abstract :
The possibility of using multivalued instead of binary linear multiple input shift registers (MISRs) for output compaction of multiple-valued logic circuits is discussed. The use of multivalued MISRs avoids the need for decoding the signals. A framework for examining aliasing in multiple-valued circular MISRs is presented. The exact aliasing probability is obtained for ternary and quaternary MISRs under an independent error model for an arbitrary test length. It is shown that multivalued MISRs perform better than their binary counterparts
Keywords :
logic circuits; logic testing; many-valued logics; shift registers; aliasing; error model; multiple input shift registers; multiple-valued logic circuits; multiple-valued test data compaction; output compaction; quaternary MISRs; ternary; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Compaction; Logic circuits; Logic testing; Very large scale integration; Wiring;
Conference_Titel :
Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on
Conference_Location :
Sendai
Print_ISBN :
0-8186-2680-1
DOI :
10.1109/ISMVL.1992.186776
