DocumentCode
2910035
Title
A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications
Author
Hoon, S.K. ; Chen, S. ; Maloberti, F. ; Chen, J. ; Aravind, B.
Author_Institution
Wireless Analog Technol. Center, Texas Instruments, Dallas, TX
fYear
2005
fDate
21-21 Sept. 2005
Firstpage
759
Lastpage
762
Abstract
This paper presents a novel two-stage low dropout regulator (LDO) that minimizes output noise via a pre-regulator stage and achieves high power supply rejection via a simple subtractor circuit in the power driver stage. The LDO is fabricated with a standard 0.35mum CMOS process and occupies 0.26 mm2 and 0.39mm2 for single and dual output respectively. Measurement showed PSR is 60dB at 10kHz and integrated noise is 21.2uVrms ranging from 1kHz to 100kHz
Keywords
CMOS integrated circuits; circuit noise; power supply circuits; system-on-chip; 0.35 micron; 1 to 100 kHz; 10 kHz; low dropout regulator; low noise high power supply rejection; output noise; power driver stage; pre-regulator stage; subtractor circuit; wireless system-on-chip application; Integrated circuit noise; Noise measurement; Personal digital assistants; Photonic band gap; Power supplies; Radio frequency; Regulators; Resistors; System-on-a-chip; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location
San Jose, CA
Print_ISBN
0-7803-9023-7
Type
conf
DOI
10.1109/CICC.2005.1568779
Filename
1568779
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