Techniques for at-speed testing of VLSI ASIC designs

This paper presents non-scan design-for-testability techniques applicable to register-transfer (RT) level data path circuits, which are usually very hard-to-test due to the presence of complex loop structures. We develop a new DFT measure, and utilize the RT-level structure of the data path together with adding constants, for cost-effective re-design of the circuit to make it easily testable, without having to either scan any FF, or break loops directly. The non-scan DFT technique was applied to several data paths. Experimental results demonstrate the feasibility of producing non-scan testable data paths, which can be tested at-speed, with marginal area overheads