Adiabatic Flip-Flops for Power-Down Applications

This paper presents adiabatic flip-flops with data-retention function, which are realized with the CPAL (complementary pass-transistor adiabatic logic) circuits using two-phase power-clocks. In the proposed flip-flops, the active enable and refresh enable terminals are added for power-gating operation. A practical sequential system with a mode-5times5times5 counter is demonstrated using the proposed power-gating scheme. Because of the two-phase scheme, the proposed flip-flops use fewer transistor count compared with four-phase adiabatic ones. SPICE simulations show that the energy loss of the adiabatic sequential circuits can be greatly reduced by shutting down idle adiabatic logic blocks.