Incremental gate: a method to compute minimal cost CCD realizations of MVL functions

n-variable vector-valued functions that map a set of vectors of integers to a set of vectors of integers are realized using logic gates constructed using charge-coupled device (CCD) very-large-scale integration (VLSI) technology. Minimal-cost realizations of these functions are obtained through an exhaustive algorithm that considers all the circuits consisting of one gate, then all the circuits consisting of two gates, and so forth. At each step all the circuits that realize functions at a cost less than the cost of any other realizations of the same functions are recorded. Since the number of functions is exponential in the number of variables and the range of integers considered, the algorithm´s time complexity is exponential in the number of variables and the range of integers. A number of pruning criteria that reduce the search space and speed up the algorithm are presented