DocumentCode
2910264
Title
Fault analysis on two-level (K +1)-valued logic circuits
Author
Wang, Hui Min ; Lee, Chung Len ; Chen, Jwu E.
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan
fYear
1992
fDate
27-29 May 1992
Firstpage
181
Lastpage
188
Abstract
A general form and a set of basic gates in implementing two-level (K +1)-valued logic circuits are presented. A complete fault analysis on the proposed circuit shows that all fanout stem faults can be collapsed to branch faults. A procedure is derived, based on the fault relationships obtained for fault collapsing. Results show that for a two-level (K +1)-valued logic circuit, faults can be reduced to 19% of the original total faults
Keywords
fault location; logic circuits; logic testing; many-valued logics; basic gates; complete fault analysis; fanout stem faults; fault analysis; fault collapsing; general form; two-level (K+1)-valued logic circuits; Circuit analysis; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Decoding; Logic circuits; Logic gates; Programmable logic arrays; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on
Conference_Location
Sendai
Print_ISBN
0-8186-2680-1
Type
conf
DOI
10.1109/ISMVL.1992.186793
Filename
186793
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