Timing-Driven Steiner Tree Construction among the Obstacles

We provide a timing-driven routing algorithm which is top-down partitioning followed by the bottom-up routing among the obstacles for each sub-region. The objective simultaneously minimizes the maximum source-to-terminal delay (abbreviated as s-t delay in the paper) and the total wirelength. First, partitioning is used to divide the chip into k irregular-size sub-regions one time by the source. According to the number of terminals in each sub-region, each sub-region is then automatically divided into k irregular-size sub-regions at most (l-1) times (i.e. the partitioned-depth of tree data structure) iteratively by the center of gravity. Third, the terminals of each sub-region are connected by the spanning graph-based method. It shows experimentally that the maximum source-to-terminal delay of the routing tree achieves 83% improvement when the source is located at the center of gravity.