Title :
SP-SOI: a third generation surface potential based compact SOI MOSFET Model
Author :
Wu, W. ; Li, X. ; Wang, H. ; Gildenblat, G. ; Workman, G. ; Veeraraghavan, S. ; McAndrew, C.
Author_Institution :
Dept. of Electr. Eng., Pennsylvania State Univ., University Park, PA
Abstract :
We report the first SOI MOSFET model that takes advantage of the recent progress in bulk MOSFET modeling. The surface-potential-based model is implemented without iterative loops, and includes physical modeling of the moderate inversion region and all small-geometry effects without relying on the traditional threshold-voltage-based formulation. The new model is verified for a 90 nm node process (40 nm polysilicon length) and is implemented in a circuit simulator
Keywords :
MOSFET; circuit simulation; silicon-on-insulator; surface potential; 40 nm; 90 nm; MOSFET; SOI; circuit simulator; node process; polysilicon; surface potential; Circuit simulation; Computational modeling; Electron mobility; Geometry; MOSFET circuits; Power supplies; Radio frequency; Solid modeling; Threshold voltage; Tunneling;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568795
