Resistance Estimation of Lateral Power Arrays through Accurate Netlist Generation

An accurate and fast technique for estimation of resistance from a large lateral power array layout along with parasitics and interconnects is presented in this paper. We extract a resistive network for metallization utilizing the finite element method (FEM). The technique benefits in terms of computation from exploitation of the repetitive nature of metallization in a power array layout. Device channels are modeled by linear resistances as the power MOS operates mostly in the linear region. Since we avoid use of lumped models or extrapolation techniques for resistance modeling, a good level of accuracy is achieved. Through a proper indexing scheme, we maintain a one-to-one correspondence between the layout geometry and the netlist from which a current profile of the layout may be formed subsequently.