Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. The proposed optimization method reduces subthreshold leakage (by 82%) and gate leakage (by 33%) in devices. Moreover, the optimization also reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 70% reduction in cell leakage and improves cell read failure probability (by 200times) compared to conventional FinFET SRAM