Title :
Tenth Annual IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No. 05TH8856)
fDate :
Nov. 30 2005-Dec. 2 2005
Abstract :
The following topics are dealt with: test, fault and error modeling; equivalence verification; system level modeling and co-design; validation test generation; Boolean satisfiability; security and coverage.
Keywords :
Boolean functions; automatic test pattern generation; computability; formal verification; high level synthesis; integrated circuit design; integrated circuit modelling; integrated circuit testing; security; Boolean satisfiability; equivalence verification; error modeling; fault modeling; formal verification; security techniques; system level co-design; system level modeling; test modeling; validation test generation;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-7803-9571-9
DOI :
10.1109/HLDVT.2005.1568800
