• DocumentCode
    2910598
  • Title

    MVP: a mutation-based validation paradigm

  • Author

    Campos, Jorge ; Al-Asaad, Hussain

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
  • fYear
    2005
  • fDate
    30 Nov.-2 Dec. 2005
  • Firstpage
    27
  • Lastpage
    34
  • Abstract
    A mutation-based validation paradigm that can handle complete high-level microprocessor implementations is presented. First, a control-based coverage measure is presented that is aimed at exposing design errors that incorrectly set control signal values. A method of automatically generating a complete set of modeled errors from this coverage metric is presented such that the instantiated modeled errors harness the rules of cause-and-effect that define mutation-based error models. Finally, we introduce an automatic test pattern generation technique for high-level hardware descriptions that solves multiple concurrent constraints and is empowered by concurrent programming.
  • Keywords
    automatic test pattern generation; concurrent engineering; fault diagnosis; formal verification; high level synthesis; logic testing; microprocessor chips; automatic test pattern generation; concurrent programming; control based coverage measure; design errors; error models; high level microprocessor implementation; high-level hardware descriptions; multiple concurrent constraints; mutation-based validation paradigm; Algorithm design and analysis; Automatic test pattern generation; Computational modeling; Data structures; Genetic algorithms; Genetic mutations; Genetic programming; Libraries; Pipelines; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
  • ISSN
    1552-6674
  • Print_ISBN
    0-7803-9571-9
  • Type

    conf

  • DOI
    10.1109/HLDVT.2005.1568809
  • Filename
    1568809