DocumentCode :
2910629
Title :
Sequential equivalence checking based on k-th invariants and circuit SAT solving
Author :
Lu, Feng ; Cheng, K.-T.
Author_Institution :
Dept. of ECE, Univ. of California at Santa Barbara, CA, USA
fYear :
2005
fDate :
30 Nov.-2 Dec. 2005
Firstpage :
45
Lastpage :
51
Abstract :
In this paper, we first present the concept of the k-th invariant. In contrast to the traditional invariants that hold for all cycles, k-th invariants guarantee to hold only after the k-th cycle from the initial state. We then present a bounded model checker BMChecker and an invariant prover IProver, both of which are based on circuit SAT techniques. Jointly, BMChecker and IProver are used to compute the k-th invariants, and are further integrated with a sequential SAT solver for checking sequential equivalence. Experimental results demonstrate that the sequential equivalence checking framework can efficiently verify large industrial designs.
Keywords :
Boolean functions; computability; formal verification; logic testing; sequential circuits; BMChecker technique; IProver technique; bounded model checker; circuit SAT solving; invariant prover; k-th invariants; sequential SAT solver; sequential equivalence checking; Algorithm design and analysis; Automata; Automatic test pattern generation; Boolean functions; Computational modeling; Data structures; Power dissipation; Sequential circuits; Signal detection; Signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
ISSN :
1552-6674
Print_ISBN :
0-7803-9571-9
Type :
conf
DOI :
10.1109/HLDVT.2005.1568812
Filename :
1568812
Link To Document :
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