Title :
Automated clock inference for stream function-based system level specifications
Author :
Talpin, Jean-Pierre ; Shukla, Sandeep Kumar
Author_Institution :
INRIA-IRISA, Rennes, France
fDate :
30 Nov.-2 Dec. 2005
Abstract :
Among system-level design frameworks and languages, system modeling approaches based on functional programming aim at rapid specification and prototyping of processing of data streams. Models constructed with functional programs provide highly modular and computationally correct models for prototyping and simulation purposes. For design space exploration, the functional programming frameworks provide semantically sound methodologies for establishing formal refinement relations and secure a trustable design automation flow. However, the stream computations expressed by functions embody an implicitly single clocked model of computation (untimed or fully synchronous) which does not take advantage of possible polychronous (multiclock) computation inherent to the system´s dataflow. To this end, we propose a type inference system for representing a synchronous and multiclocked model of computation in the typed and functional programming language ML. Along the way, we address the issue of performing the automated refinement of implicitly timed stream functions in a model of computation that supports reasoning on partially ordered signal clocks, allowing for formal design transformation and verification to be performed in the context of a functional programming environment.
Keywords :
clocks; formal specification; functional programming; logic CAD; automated clock inference; design automation flow; design space exploration; formal design transformation; formal refinement; formal verification; functional programming; multiclocked model; partially ordered signal clocks; stream computations; synchronous model; system level specifications; system modeling; timed stream functions; Clocks; Computational modeling; Context modeling; Design automation; Functional programming; Prototypes; Signal design; Space exploration; System-level design; Virtual prototyping;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
Print_ISBN :
0-7803-9571-9
DOI :
10.1109/HLDVT.2005.1568815