• DocumentCode
    2910759
  • Title

    Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model

  • Author

    Shih, Che-Hua ; Huang, Juinn-Dar ; Jou, Jing-Yang

  • Author_Institution
    Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan
  • fYear
    2005
  • fDate
    30 Nov.-2 Dec. 2005
  • Firstpage
    87
  • Lastpage
    93
  • Abstract
    Verifying if an integrated component is compliant with certain interface protocol is a big issue in component-based SOC designs. Massive constrained random simulation stimuli are becoming crucial to achieve a high verification quality. To further improve the quality, the stimulus biasing technique should be used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the nondeterministic extended finite state machine (NEFSM), and then propose an automatic stimulus generation approach based on the NEFSM. This approach is capable of providing numerous biasing options. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.
  • Keywords
    circuit CAD; finite state machines; integrated circuit design; logic CAD; protocols; automatic stimulus generation; interface protocol verification; nondeterministic extended finite state machine; random simulation stimulus; stimulus biasing; Acceleration; Automata; Binary decision diagrams; Boolean functions; Controllability; Data structures; Design engineering; Process design; Protocols; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2005. Tenth IEEE International
  • ISSN
    1552-6674
  • Print_ISBN
    0-7803-9571-9
  • Type

    conf

  • DOI
    10.1109/HLDVT.2005.1568819
  • Filename
    1568819