DVGen: a test generator for the transmeta Efficeon VLIW processor

This paper describes DVGen, a tool that significantly improves the productivity of the verification engineer by facilitating the generation of self-checking tests from high-level specifications of test intent. DVGen automates resource management, instruction scheduling and computation of self-check reference values, allowing the engineer to focus on test intent through minimally-constrained specifications. It provides the control afforded by writing tests in assembly language as well as the power and flexibility afforded by writing tests in a high-level language. This paper details the scheduling of instructions and the methods of controlling code generation. The power of DVGen´s interface with the architectural reference simulator is explored. Techniques employed by DVGen to perturb test generation in order to increase coverage from existing test specifications are presented. Following that, the ability of DVGen to combine diverse specifications intelligently in order to create tests that setup and trigger concurrent interesting events is discussed. The paper concludes with a high-level discussion of DVGen´s most salient features.