A programmable VLC core architecture for video compression DSP

Author

Fukuzawa, Yuji ; Hasegawa, Kouichi ; Hanaki, Hirokazu ; Iwata, Eiji ; Yamazaki, Takao

Author_Institution

Media Process. Labs., Sony Corp., Tokyo, Japan

fYear

1997

fDate

3-5 Nov 1997

Firstpage

469

Lastpage

478

Abstract

A programmable Variable-Length Coder/decoder, “VLC core”, is developed for various video compression algorithms and standards. This paper describes the programmable architecture that allows the coding and the decoding process to be performed by the same logical units on a small chip. This VLC core is the first coder and decoder which shares the table memory, the barrel shifter and the code buffer for coding and decoding with sufficient programmability for MPEG 1, 2 and H.261

Keywords

data compression; decoding; digital signal processing chips; variable length codes; video coding; MPEG; barrel shifter; code buffer; decoding; programmable VLC core architecture; table memory; variable-length coder/decoder; video compression DSP; Codecs; Decoding; Digital signal processing; Digital signal processors; Hardware; Laboratories; Signal processing algorithms; Standards development; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on

Conference_Location

Leicester

ISSN

1520-6130

Print_ISBN

0-7803-3806-5

Type

conf

DOI

10.1109/SIPS.1997.626321

Filename

626321

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2912010