Methods for partitioning the system and performance evaluation in power-hardware-in-the-loop simulations. Part I

In this paper, the interfacing schemes for power-hardware-in-the-loop (PHIL) simulations are studied. In Part I, different simulation/hardware interfaces are introduced, and a novel interfacing scheme based on the time-variant first-order approximation of dynamics of the hardware under test (HUT) is proposed. The performances of different interfaces are compared through the decoupled simulation of first-order systems. More advanced performance evaluation methods are introduced in part II.