A design and manufacturing solution for high reliable non-leaded CSP´s like QFN

The ongoing miniaturization and increasing functionality of electronic equipment have forced the semiconductor industry to develop smaller and thinner devices in ever-shorter cycles. The trend to chip scale area/perimeter array packages is more than obvious. One of these miniaturized IC packages, first presented by Matsushita under the name QFN (also called MLF, LPCC, QLP or VQFN), has rapidly become popular. One concern is the limited device reliability (JEDEC moisture level 3). Very rapidly implemented miniaturization in the past has led to reduced device reliability, as in the case of the “popcorn phenomenon” from which thin devices such as PBGA, TQFP, TSOP, etc., suffer. In addition, increasing time to market pressure forces the industry to shorten the package design time. Under this pressure, the complexity and link between package manufacturability and device reliability is sometimes neglected. The resulting dissatisfaction has led to a design and manufacturing process research program, targeting best board assembly quality and a reliability performance level of at least JEDEC-moisture level 1. By carefully analyzing all the constraints which limit the device and board assembly quality of such new devices by using all past experiences and by considering the capabilities of existing and well established assembly and packaging technologies, it should be possible to build and economically manufacture such devices in high volume, achieving the required board assembly quality and device reliability in the requested cost frame