DocumentCode :
291296
Title :
An evolutionary method for automatic wire routing
Author :
Tanomaru, J. ; Oka, K.
Author_Institution :
Dept. of Inf. Sci., Tokushima Univ., Japan
Volume :
2
fYear :
1994
fDate :
5-9 Sep 1994
Firstpage :
1117
Abstract :
This paper introduces an automatic wire routing (AWR) algorithm based on evolutionary principles. In the proposed algorithm (dubbed EWRA, where “E” stands for evolutionary), populations of wiring networks evolve through the action of stochastic operators conceived from the heuristics of manual wire-routing. In each wiring configuration (individual of the population), all nets are routed and temporary intersections are allowed. The objective of evolution is to improve wiring quality in the sense of eliminating unwanted net intersections and simplifying paths in order to reduce manufacturing costs and increase reliability. Although the populations approach and the use of stochastic operators for simulating evolution resemble conventional genetic algorithms (GAs) operation, the AWR problem requires much more advanced representation and sophisticated operators whose action takes place at the wiring level, and not at the string level. Results showing the effectiveness of the proposed algorithm in a serial implementation are presented. Furthermore, in order to reduce computation time, parallel implementation of the proposed AWR algorithm is discussed for an ideal multicomputer architecture and for a realistic binary-tree multicomputer, in which the algorithm is currently being implemented. Preliminary results indicate that the proposed EWRA is feasible for AWR applications and suggest that efficient implementations can be obtained by using massively parallel processing
Keywords :
circuit layout; circuit layout CAD; genetic algorithms; heuristic programming; multiprocessing systems; binary-tree multicomputer; eliminating unwanted net intersections; evolutionary automatic wire routing; genetic algorithms; heuristics; manufacturing costs reduction; massively parallel processing; multicomputer architecture; parallel implementation; reliability; serial implementation; temporary intersections; Computer architecture; Concurrent computing; Costs; Genetic algorithms; Manufacturing; Parallel processing; Routing; Stochastic processes; Wire; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Industrial Electronics, Control and Instrumentation, 1994. IECON '94., 20th International Conference on
Conference_Location :
Bologna
Print_ISBN :
0-7803-1328-3
Type :
conf
DOI :
10.1109/IECON.1994.397948
Filename :
397948
Link To Document :
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