A multiprocessor system for AUV applications

Autonomous Underwater Vehicles (AUV´s) require high processing throughput and fault tolerance combined with low power and volume. High throughput is directly related to mission complexity and the degree of vehicle autonomy. Complex acoustic and optical sensors must be interpreted in real time and decisions based on uncertain data must be formulated and executed. Unexpected occurrances including environmental anomalies and enemy threats force immediate action and revised tactical mission planning. The development of the Autonomous Command and Control Demonstration (ACCD) system as a component development of the Autonomus Underwater Vehicle (AUV) program by Lockheed Advanced Marine Systems (AMS) has estimated peak rates greater than 100 MIPS are required for Command and Control processing. The processing itself will be a combination of signal, algorithmic and symbolic processing. Both deterministic and probabalistic algorithms will require computation. For vehicle operations in a fully autonomous mode, any component failures must be corrected by an automated fault tolerant system. The AUV software architecture, developed as part of a detailed analysis, established the performance requirements for the Command and Control hardware. The characteristics of various hardware architectures such as distributed, common memory, data flow, systolic, and connection type systems were established and assessed to determine the hardware best suited to the software structure. A heterogeneous hypercube was found to be optimum. The hypercube is reconfigurable for fault tolerance, is flexible, and can achieve high throughputs with low power and without special cooling systems. AMS will use a commercially-available hypercube as the basis of their Command and Control Architecture for an Unmanned Underwater Vehicle. This hypercube has a 32 bit architecture, extremely high message passing capability and will have image processing accelerators working in conjunction with standard cube nodes. Both symbolic and algorithmic processing will take place on the standard nodes. In this paper, system requirements, software hierarchy, computer architecture analysis and the resulting hypercube design will be discussed in detail.