VLSI Circuit Test Vector Compression Technique

A new test vector compression method for VLSI circuit testing is presented in this paper. The technique is essentially software-based, where a program is loaded into the on-chip processor memory along with the compressed test data sets. To reduce the on-chip storage area and testing time, the large volume of test data is first compressed before downloading into the on-chip processor. The proposed method utilizes a set of adaptive coding techniques for achieving lossless compression. The compression program need not be loaded into the embedded processor, as only the decompression of the test data is is necessary for application by the automatic test equipment (ATE). The technique requires minimal hardware overhead, while the on-chip processor core can be reused for normal operation after testing. The feasibility of the developed approach has been demonstrated through extensive simulation experiments on ISCAS 85 and ISCAS 89 benchmark circuits.