Application of SU-8 in flip chip bump micromachining for millimeter wave applications

There has been considerable interest in the development of SU-8 ^TM thick negative photoresist for complex micromachined structures. In this paper, we evaluate a recent implementation of this photoresist for electroplating of high aspect ratio interconnect bumps using a prototype problem which is relevant to the mass production of bumped RF MMICs. This alternative technique appears to be conceptually simpler than the conventional method of etching, is easier to implement, and causes no degradation in accuracy; in fact, it seems to achieve a specified level of high aspect ratio performance more efficiently. This is in contrast to results from conventional photolithography, where very low substrate to device stand-offs are normal. Simulation of plated bump interconnects is found to be consistent with test demonstrators, which verifies the correctness of our new approach. These findings are encouraging from a volume assembly economy perspective and they suggest that the SU-8/electroplating concept is an excellent choice for MMIC attach in volume manufacture. The results demonstrate that SU-8 development time is the strongest determinant of process accuracy, with increasing errors occurring with underexposed SU-8 and short development time. The optimum process path for SU8 on silicon is reported