Virtual thermo-mechanical prototyping of electronic packaging-the bottlenecks and solutions for damage modeling

Author

Zhang, G.Q. ; Tay, A.A.O. ; Ernst, L.J.

Author_Institution

CFT/Philips, Eindhoven, Netherlands

fYear

2000

fDate

2000

Firstpage

263

Lastpage

269

Abstract

This paper presents the strategy and methodology for virtual thermo-mechanical prototyping of electronic packages specified by Philips. The focus is on the bottlenecks and solutions for damage modeling in virtual thermo-mechanical prototyping. It demonstrates that the capability to understand and develop reliable damage models and criteria at both macro and micro levels is vital for virtual thermo-mechanical prototyping. As a conclusion, by combining the strengths of reliable simulation models with an advanced optimization strategy, virtual prototyping can be used in packaging development to achieve greater business profitability

Keywords

chip-on-board packaging; circuit optimisation; circuit simulation; flip-chip devices; integrated circuit interconnections; integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; plastic packaging; product development; soldering; FCOB; business profitability; damage criteria; damage modeling; damage modeling bottlenecks; electronic packaging; flip chip; macro level models; micro level models; optimization strategy; packaging development; plastic IC packaging; reliable damage models; reliable simulation models; solder; virtual prototyping; virtual thermo-mechanical prototyping; Consumer electronics; Design methodology; Electronic packaging thermal management; Electronics industry; Electronics packaging; Optimization methods; Profitability; Prototypes; Thermomechanical processes; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference, 2000. (EPTC 2000). Proceedings of 3rd

Print_ISBN

0-7803-6644-1

Type

conf

DOI

10.1109/EPTC.2000.906384

Filename

906384