DocumentCode
2913297
Title
Flip chip pad structure for high density organic build up substrate
Author
Nakamura, Kenshi ; Harazono, Masaaki ; Yamashita, Hiroyuki ; Ding, D.H. ; Baker, Junaida ; Dubey, Anamika
Author_Institution
Kyocera Corp., Kagoshima, Japan
fYear
2000
fDate
2000
Firstpage
283
Lastpage
285
Abstract
There has been a growing demand for high-density organic flip chip packages for high performance IC due to lower cost and lower electrical noise. The paper presents studies conducted in order to achieve high adhesion between the flip chip pads and the insulation layer on the organic substrate. Simulation studies on the stress at both SMD (solder mask defined) and NSMD (nonsolder mask defined) flip chip pads were performed. The SMD structure was found to have lower stress at the edges between the Cu pad and insulation layer. The simulation result was confirmed by chip pull tests on the actual samples. Most of the solder joints on the SMD samples showed breakage at the solder joints after the test (taffy mode) and the pull strength was above the required standard. As for NSMD, the Cu pads were lifted from the resin during the test and the pull strength was much lower than SMD samples
Keywords
adhesion; chip-on-board packaging; circuit simulation; flip-chip devices; fracture; insulating thin films; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; internal stresses; soldering; stress analysis; Cu; Cu pad/insulation layer edge stress; IC performance; NSMD flip chip pads; SMD flip chip pads; SMD structure; adhesion; chip pull tests; electrical noise; flip chip pad structure; flip chip pads; high density organic build up substrate; insulation layer; nonsolder mask defined flip chip pads; organic build up substrate; organic flip chip packages; organic substrate; package cost; pull strength; solder joint breakage; solder joint test; solder joints; solder mask defined flip chip pads; stress simulation; Adhesives; Costs; Flip chip; Insulation; Integrated circuit noise; Integrated circuit packaging; Resins; Soldering; Stress; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2000. (EPTC 2000). Proceedings of 3rd
Print_ISBN
0-7803-6644-1
Type
conf
DOI
10.1109/EPTC.2000.906387
Filename
906387
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