Design of monitored self-checking sequential circuits for enhanced fault models

Author

Parekhji, R.A. ; Venkatesh, G. ; Sherlekar, S.D.

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India

fYear

1993

fDate

16-18 Nov 1993

Firstpage

298

Lastpage

303

Abstract

This paper discusses the design of monitored self-checking sequential circuits for the detection of single and multiple unidirectional stuck-at faults, as well as delay faults. It is shown how the monitoring machine approach provides a uniform error detection mechanism for the detection of these faults. Designs based on this method are shown to compare favourably, in terms of hardware overheads and fault coverage, with previous self-checking implementations based on restricted fault models

Keywords

automatic testing; delays; design for testability; fault diagnosis; logic design; logic testing; sequential circuits; FSM; delay faults; enhanced fault models; fault coverage; hardware overheads; logic design; monitored self-checking sequential circuits; monitoring machine; multiple unidirectional stuck-at faults; single fault detection; uniform error detection; Circuit faults; Computer science; Computerized monitoring; Condition monitoring; Delay; Design engineering; Design methodology; Electrical fault detection; Fault detection; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1993., Proceedings of the Second Asian

Conference_Location

Beijing

Print_ISBN

0-8186-3930-X

Type

conf

DOI

10.1109/ATS.1993.398821

Filename

398821