Design of Testing Struture in Microprocessor Based on JTAG

With the development of integrated circuit technology, it is more difficult to test and debug. Usually, design for testability (DFT) and debugging structure are made separately in VLSI, which need a great deal of additional hardware resource. This paper introduces a testing structure designed in microprocessor based on JTAG, which is based on scan-set technology, combined with the boundary scan and internal scan technology. This testing structure integrates with DFT and debugging logic, which avoids many scan chains hardware expenses and reduces the cost of design and verification. This structure can supply high fault coverage near 100%, and debugging ability through JTAG port, which only increases the difficulty of the circuit logic design and is applicable to all general-purpose microprocessor chips.