DocumentCode
2914527
Title
Fast algorithm for 4-qubit reversible logic circuits synthesis
Author
Li, Zhiqiang ; Chen, Hanwu ; Xu, Baowe ; Liu, Wenjie ; Song, Xiaoyu ; Xue, Xilin
Author_Institution
Sch. of Comput. Sci. & Eng., Southeast Univ., Nanjing
fYear
2008
fDate
1-6 June 2008
Firstpage
2202
Lastpage
2207
Abstract
Owing to the exponential nature of the memory or run-tune complexity, many existing methods can only synthesize 3-qubit circuits, however, (G.W. Yang et al., 2005) can achieve 12 steps for the CNP (controlled-Not gate, NOT gate and Peres gate) library in 4-qubit circuit synthesis with mini-length by using an enhanced bi-directional synthesis approach. We mainly absorb the ideas of our 3-qubit synthesis algorithms based on hash table and present a novel and efficient algorithm which can construct almost all optimal 4-qubit reversible logic circuits with various types of gates and mini-length cost based on constructing the shortest coding and the specific topological compression, whose lossless compression ratios of the space of n-qubit circuits is near 2timesn!. Our algorithm has created all 3120218828 optimal 4-qubit circuits whose length is less than 9 for the CNT (Toffoli gate) library, and it can quickly achieve 16 steps through cascading created circuits. To the best of our knowledge, there are no other algorithms to achieve the contribution.
Keywords
logic CAD; network topology; 4-qubit reversible logic circuits synthesis; controlled-Not gate; enhanced bidirectional synthesis approach; hash table; lossless compression ratios; run-tune complexity; topological compression; Circuit synthesis; Evolutionary computation; Logic circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Evolutionary Computation, 2008. CEC 2008. (IEEE World Congress on Computational Intelligence). IEEE Congress on
Conference_Location
Hong Kong
Print_ISBN
978-1-4244-1822-0
Electronic_ISBN
978-1-4244-1823-7
Type
conf
DOI
10.1109/CEC.2008.4631091
Filename
4631091
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