Timing Error Calibration in Time-Interleaved ADC by Sampling Clock Phase Adjustment

Timing error between sampling and holding (SZH) channels for Time-interleaved analog-to-digital converts (TiADCs) is caused by clock skew and RC (sampling resistance and capacitance) mismatch. This paper presents the measurement results of a prototype chip based on our previous work (Z. Liu et al., 2006), in which we showed timing error due to clock skew and RC mismatch can be calibrated simultaneously by adjusting the clock phase. The results show that the residue timing error can be reduce to 1-ps.