Fitness functions for the unconstrained evolution of digital circuits

This work is part of a project that aims to develop and operate integrated evolvable hardware systems using unconstrained evolution. Experiments are carried out on an evolvable hardware platform featuring both combinatorial and registered logic as well as sequential feedback loops. In order to be able to accurately assess the transient output of the system and at the same time speed up evolution, new fitness evaluation methods are introduced. These bitwise and hierarchical fitness evaluation methods are adapted and further developed specifically for hardware implementation. It is shown that the newly developed approaches are particularly powerful in coping with two important issues: computational ambiguities, which generally occur when evaluating binary strings, and transient effects resulting from measuring hardware output. On two combinatorial problems it is shown that the new fitness functions improve the performance of evolution and allow stable solutions to be found more reliably. The experiments are carried out with a recently developed hardware platform called reconfigurable integrated system array (RISA).