DocumentCode :
2915910
Title :
A Hardware Oriented, Low-Complexity LORD MIMO Detector
Author :
Tomasoni, Alessandro ; Ferrari, Marco ; Bellini, Sandro ; Siti, Massimiliano ; Cupaiuolo, Teo
Author_Institution :
Politec. di Milano, Milan, Italy
fYear :
2010
fDate :
23-27 May 2010
Firstpage :
1
Lastpage :
5
Abstract :
In this paper we introduce an innovative version of the recently proposed Layered ORthogonal lattice Detector (LORD). LORD is an attractive MIMO detection algorithm, which aims to approach the optimal Maximum-Likelihood (ML) detection performance with a reasonable complexity, quadratic in the number of transmitting antennas rather than exponential. LORD is also well suited to a hardware (e.g. ASIC or FPGA) implementation because of its regularity, deterministic latency and parallelism. Nevertheless, its complexity is still high in case of high cardinality constellations, such as the 64-QAM foreseen by the 802.11n standard. We show that, when only global latency constraints exist, e.g. a fixed time to detect the whole OFDM symbol, the LORD complexity can be remarkably reduced (up to 60%), still approaching the ML performance.
Keywords :
MIMO communication; OFDM modulation; communication complexity; maximum likelihood detection; transmitting antennas; LORD MIMO detection; LORD complexity; ML performance; OFDM symbol; deterministic latency; global latency constraint; high cardinality constellation; layered orthogonal lattice detector; optimal maximum-likelihood detection; parallelism; transmitting antenna; Application specific integrated circuits; Delay; Detection algorithms; Detectors; Field programmable gate arrays; Hardware; Lattices; MIMO; Maximum likelihood detection; Transmitting antennas;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications (ICC), 2010 IEEE International Conference on
Conference_Location :
Cape Town
ISSN :
1550-3607
Print_ISBN :
978-1-4244-6402-9
Type :
conf
DOI :
10.1109/ICC.2010.5502815
Filename :
5502815
Link To Document :
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