Title :
Design of low power current-mode flash ADC
Author :
Bhat, M.S. ; Rekha, S. ; Jamadagni, H.S.
Author_Institution :
Centre for Electron. Design & Technol., Indian Inst. of Sci., Bangalore, India
Abstract :
The design of a high-speed current-mode CMOS flash analog-to-digital converter (ADC) is presented. For high-speed operation, current mirroring technique with current comparison architecture is used and its advantages and limitations are explained. The optimization procedure is aimed at minimizing static power consumption, and its impact on circuit performance is investigated. A maximum sampling speed of 80 Ms/sec is achieved at 78 mW power consumption. The ADC is designed using 0.7-μm CMOS technology.
Keywords :
CMOS integrated circuits; analogue-digital conversion; optimisation; power consumption; 78 mW; current mirroring technique; current-mode CMOS flash analog-to-digital converter; optimization; power consumption; Analog-digital conversion; CMOS process; CMOS technology; Circuit optimization; Current mode circuits; Energy consumption; Impedance; Sampling methods; Threshold voltage; Very large scale integration;
Conference_Titel :
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN :
0-7803-8560-8
DOI :
10.1109/TENCON.2004.1414914
