• DocumentCode
    2916560
  • Title

    Hybrid algorithm for bisection circuit partitioning

  • Author

    Yodtean, Apiradee ; Chantngarm, Peerasak

  • Author_Institution
    Thailand IC Design Incubator, Pathumwan Inst. of Technol., Thailand
  • Volume
    D
  • fYear
    2004
  • fDate
    21-24 Nov. 2004
  • Firstpage
    324
  • Abstract
    This paper presents a new algorithm, hybrid algorithm (HA), to improve the performance in circuit partitioning while using less resources. Although there have already been two circuit partitioning techniques widely used, SA and GA, each of them have advantages and disadvantages. On the one hand, SA does not requires much memory but takes a lot of time to perform. On the other hand, GA performs faster but needs more memory. The proposed algorithm combines both of them together and produces a superior result. It improves the speed while using moderate storage. HA starts from finding an initial solution from a relatively good candidate solution. Then a new solution is created through mutation and the cost function of the new solution is compared with that of the initial solution. After the algorithm makes a decision to keep the old solution or the new one, a newer solution is created again and the cost function is compared with that of the formerly selected solution. This process will iterates until the temperature becomes zero. Experiments were done on a PC using hypergraphs from ISPD98 Circuit Benchmark Suite. SA, GA and our proposed algorithm are run on the benchmark to compare average cost function, minimum cost function and average CPU time. The results show the superior performance of HA compared to the traditional optimization techniques.
  • Keywords
    costing; genetic algorithms; integrated circuits; microcomputers; power engineering computing; simulated annealing; GA; ISPD98 Circuit Benchmark Suite; PC; SA; bisection circuit partitioning; cost function; decision making; genetic algorithm; hybrid algorithm; hypergraph; iteration process; optimization technique; simulated annealing algorithm; Algorithm design and analysis; Cost function; Design engineering; Genetic mutations; Hybrid integrated circuits; Partitioning algorithms; Peer to peer computing; Simulated annealing; System-on-a-chip; Telecommunication computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2004. 2004 IEEE Region 10 Conference
  • Print_ISBN
    0-7803-8560-8
  • Type

    conf

  • DOI
    10.1109/TENCON.2004.1414935
  • Filename
    1414935