Algorithm for low power combinational circuit testing

Power dissipation during testing of VLSI circuits is major concern due to the switching activity of the circuit under test. In this paper, a novel method is presented, that aims at reducing total power consumption in combinational circuit during testing. This is achieved by minimizing the switching activity of the circuit by reducing the Hamming distance between successive test vectors. The test vectors are generated with don´t care for particular circuit. These vectors are reordered for minimum total hamming distance. Don´t care bits of these vectors are replaced by appropriate value 1 or 0 so that the total number of transitions between two vectors is minimum. Then the same vector set is used for testing. Thus the reordered test vector set reduces testing power without affecting the fault coverage. Experimental results of the proposed method with ISCAS85 benchmark circuits show that the switching activity can be reduced up to 35 % when compared to the previous research paper of this work (K. Paramasivam, et al., 2004) and reduced up to 91 %.