Evaluation of a clocking strategy with relaxed constraints on clock edges

A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.