DocumentCode :
2917059
Title :
Low complexity Reed-Solomon encoder using globally optimized finite field multipliers
Author :
Jittawutipoka, J. ; Ngarmnil, J.
Author_Institution :
Electron. Eng. Dept., Mahanakorn Univ. of Technol., Thailand
Volume :
D
fYear :
2004
fDate :
21-24 Nov. 2004
Firstpage :
423
Abstract :
This paper proposes a new approach to implement a low complexity Reed-Solomon (RS) encoder of DTV systems. Based on a reported optimization algorithm which yields low complexity constant finite field multipliers for Galois fields GF(2n), the new compact RS encoder is constructed with 15 optimized finite field multipliers, of which the redundant operations are reduced to minimize the number of modulo 2 additions or XOR gates. Hence the 15 multipliers partly share the same hardware operations. A significant improvement on complexity is clearly shown with FPGA implementation.
Keywords :
Galois fields; Reed-Solomon codes; digital video broadcasting; field programmable gate arrays; logic gates; multiplying circuits; optimisation; DTV systems; FPGA implementation; Galois field; Reed-Solomon encoder; XOR gates; constant finite field multipliers; digital TV system; optimization algorithm; redundant operation; Galois fields; Reed-Solomon codes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN :
0-7803-8560-8
Type :
conf
DOI :
10.1109/TENCON.2004.1414960
Filename :
1414960
Link To Document :
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