Comparator based self-trim and self-test scheme for arbitrary analogue on-chip values

Trimming is a ubiquitous element of many mixed-signal circuits. Already a long standing requirement of mixed-signal design trimming is made even more popular by shrinking design geometries with their associated variability make trimming even more popular. With increasing demand of trimming per chip, the ATE based trimming process is moved on-chip. The comparator based self-trim is the most common base for self-trim circuits due to its minimum overhead. Yet self-trim is not identical to self-test. Introduction of a simple fault model shows the blindness of the industrially important comparator based self-trimming to manufacturing faults. In order to preserve the simplicity of the comparator based trimming, a scheme is proposed which allows a complete self-test of both the comparator and the trim result. The paper also investigates the characteristics of the self-trimmed distribution and its consequences for the self-test scheme. Simulation and silicon results from industrial designs are presented.