DocumentCode
2917496
Title
2-D DCT using on-line arithmetic
Author
Bruguera, Javier ; Lang, Tomas
Author_Institution
Dept. of Electron., Santiago de Compostela Univ., Spain
Volume
5
fYear
1995
fDate
9-12 May 1995
Firstpage
3275
Abstract
Presents a VLSI architecture for the evaluation of the (8×8)-point 2-D DCT with on-line arithmetic. The utilization of on-line arithmetic, in combination with an algorithm based on FCT and matrix multiplication, reduces the total hardware maintaining a data rate and a latency similar to approaches based on distributed or parallel arithmetic. The architecture has been integrated in a chip using a 1 μ CMOS technology, occupying an area of 56.7 mm2
Keywords
CMOS digital integrated circuits; VLSI; data compression; digital arithmetic; digital signal processing chips; discrete cosine transforms; matrix multiplication; transform coding; video coding; 1 micron; 2-D DCT; CMOS technology; VLSI architecture; data rate; latency; matrix multiplication; on-line arithmetic; Arithmetic; CMOS technology; Computer architecture; Delay; Discrete cosine transforms; Hardware; Image coding; Matrix decomposition; Transform coding; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., 1995 International Conference on
Conference_Location
Detroit, MI
ISSN
1520-6149
Print_ISBN
0-7803-2431-5
Type
conf
DOI
10.1109/ICASSP.1995.479584
Filename
479584
Link To Document