Hybrid Algorithm for Floorplanning Using B*-tree Representation

Floorplanning is an important step in the physical design of VLSI circuits. Since the variety of packing is uncountable, it is hard to be solved exactly in practical applications. The key issue is how to find the optimal solution in the finite solution space. In this paper, we proposed hybrid algorithm which based on B*-tree representation to improve the area utilization. The simulated annealing was embedded into tabu search for floorplanning. Experimental results show that our approach can improve the area utilization in shorter time. As we can see from the experimental results, we can improve area utilization and obtain the optimal results in a short runtime. It shows that the method we proposed is effective and efficient.