Architecture and design synthesis of 2.5 Gsamples/s 4-b pipelined flash ADC in SoC applications

This paper presents an architecture and design synthesis of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC designed in 130 nanometer CMOS technology has superior performance of sampling rate of 2.5 GHz for an input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC.