Title :
Architecture and design synthesis of 2.5 Gsamples/s 4-b pipelined flash ADC in SoC applications
Author :
Wang, Mingzhen ; Chen, Chien-In Henry
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
This paper presents an architecture and design synthesis of a 4-bit pipelined flash analog-to-digital converter (ADC). The preliminary results show the ADC designed in 130 nanometer CMOS technology has superior performance of sampling rate of 2.5 GHz for an input signal bandwidth of 1 GHz. For the purpose of design reuse, a general architecture and synthesis flow of the ADC is proposed. One of such work is about solution of a long-standing open problem on the design synthesis of high-performance ADC.
Keywords :
CMOS integrated circuits; analogue-digital conversion; signal sampling; 4-bit pipelined flash ADC; CMOS technology; SoC application; analog-to-digital converter; architecture synthesis; design synthesis; sampling rate; signal bandwidth; CMOS technology; Clocks; Delay; Digital signal processing chips; Integrated circuit synthesis; Radio frequency; Sampling methods; Signal design; Signal synthesis; System-on-a-chip;
Conference_Titel :
Industrial Electronics Society, 2005. IECON 2005. 31st Annual Conference of IEEE
Print_ISBN :
0-7803-9252-3
DOI :
10.1109/IECON.2005.1569249
