Title :
Dynamic Partial Reconfiguration in FPGAs
Author :
Lie, Wang ; Feng-yan, Wu
Author_Institution :
Dept. of Comput. Sci. & Electron. Inf., Guangxi Univ., Nanning, China
Abstract :
Dynamic partial reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the advantages of the newest dynamic partial reconfiguration design flow.
Keywords :
field programmable gate arrays; hardware description languages; reconfigurable architectures; FPGA; dynamic partial reconfiguration; early access partial reconfiguration; Aerospace industry; Application software; Computer science; Field programmable gate arrays; Hardware; Information technology; Logic devices; Reconfigurable logic; Routing; Table lookup; Dynamic Partial Reconfiguration(DPR); Early Access Partial Reconfiguration(EAPR); FPGA;
Conference_Titel :
Intelligent Information Technology Application, 2009. IITA 2009. Third International Symposium on
Conference_Location :
Nanchang
Print_ISBN :
978-0-7695-3859-4
DOI :
10.1109/IITA.2009.334
